Emulation Engineer – A003802

Location: Campbell, CA, USA

Job Type: Full Time Employee

Career Level: Experienced

 

Primary Responsibilities

Work as part of a team responsible for managing the emulation of SoCs (partial or whole) in Synopsys's Zebu. As a member of a team will be responsible for partitioning/ top level arrangement of the RTL design to become suitable for emulation, writing scripts to manage the process of preparation for emulation and the interface with the tool-chain.    

 

Required Skills and Experiences

  • Extensive knowledge of Verilog, System Verilog and Python, extensive knowledge of hardware assisted ASIC verification prototyping, emulation , good knowledge of FPGA debug, working knowledge of Xilinx and Altera based FPGA's tools, work experience with Verification methodologies (UVM/OVM), working experience with RTL Simulators such as VCS.
  • Minimum education level required: BSEE with min of five years work experience, MSEE with three years of work experience.

 

Desired Skills

  • Extensive knowledge of System on Chip (SOC) with multi-core processors, Verilog, SystemVerilog, and standard scripting languages utilized in ASIC design tool-chain
  • C/ C++ programming is a plus
  • Ability to work with a multi-site team