Video courses cover the MIPS architecture and software interfaces
This video course covers the basic MIPS architecture and related software interfaces. It is intended for software programmers who will be doing boot code and device drivers.
The course covers: Software tools, the MIPS instruction set, assembly language coding, the MIPS memory map, programming a TLB, exceptions and interrupts, caches, scratch pad RAM, CPU initialization code, power management, and MIPS specific C. porting needs.
This class is designed for Software programmers. It will give you an understanding of the additional programming interfaces for a MIPS Coherent Processing system. This course covers an overall description of the Coherent Processing System, Global Configuration Registers, Global interrupt controller, Cluster Power Controller Booting a CPS system and Segmentation Control and EVA.
This class is intended for programmers. It covers programming extensions needed for a Multi-Threading Core. The course includes sections on Fine Grain multi-threading, additional CP0 register usage, additions to the instruction set for multi-threading, Inter-thread communication, and the Policy Manager (QOS). The class shows code examples of the major elements needed to program a Multi Threading MIPS core.