System on Chip Architect – A001250

Location: Campbell, CA, USA

Job Type: Full Time Employee

Career Level: Experienced


Primary Responsibilities

Responsible for SoC architecture spanning RTL design, integration, microarchitecture, power optimization, IP selection, area optimization, logic synthesis, timing constraints development, power/clock architecture, timing closure, ECO and tapeout. This role will interface with internal and external design groups. Participate in design/architecture reviews, design verification plans, emulation/co-validation planning, establishing & defining RTL and physical design methodologies and flow automation. This role requires strong technical leadership and decision-making skills and the ability to influence across the Baseband ASIC core team as well as other functional teams.


Required Skills and Experiences

  • The successful candidate will have excellent communication and leadership skills, experience having managed architecture, RTL and/or PD engineering teams, a proven ability to develop and drive technical execution plans with challenging schedules, experience with RTL Logic Design of multi-million gate ASICs/ modem ASIC implementation in complex VLSI, experience with high speed, low power designs with proficiency in front end tools and methodologies, various CPU and DSP architectures with prior experience with CPU & IP Integration PCIe controllers, DDR memory controllers, DMAs,high speed interfaces, SoC bus protocols, emulation/Co-validation and Physical Design leading to tape-out, DFT methodologies, placement and route, clock tree synthesis, gate-level simulations, STA and timing sign-off.
  • Minimum education level required: MSEE with min of ten years work experience, PhD with five years of work experience.


Desired Skills

  • Extensive knowledge of System on Chip (SOC) with multi-core processors, Verilog, SystemVerilog, and standard scripting languages utilized in ASIC design tool-chain
  • C/ C++ programming is a plus
  • Ability to work with a multi-site team