System on Chip Architect – A001250
Location: Campbell, CA, USA
Job Type: Full Time Employee
Career Level: Experienced
Wave Computing is seeking a Senior System on Chip Architect, to lead design and specification of our next generation DPU, for deep learning.
Wave Computing is revolutionizing the deep learning industry by enabling organizations to drive better business value from their data with its roadmap of WaveFlow™ computing systems. The company’s innovative system solutions based upon dataflow technology provide high-performance training and high-efficiency inferencing at scale, bringing deep learning to customers’ data wherever it may be. Wave Computing was named a Machine Learning Industry Technology Innovation Leader by Frost & Sullivan, and a Top 25 Artificial Intelligence Provider by CIO Application Magazine.
- Lead the design, specification of our performance analysis of our next generation DPU.
- Responsible for runtime software architecture and network on a chip.
- Custom IP blocks for Deep Learning, IP selection, DFT, memory controllers, integrated processor and I/O controllers.
- Documentation of architecture spec and reviews etc.
- Work with product marketing, verification, software and systems teams, to ensure that the SOC meets requirements.
- Design for test.
Required Skills and Experiences
- The ideal candidate will have experience leading the architecture, specification of an entire SOC architecture in deep sub-micron.
- The successful candidate will have excellent communication and leadership skills, experience having managed architecture, RTL and/or PD engineering teams, a proven ability to develop and drive technical execution plans with challenging schedules, experience with RTL Logic Design of multi-million gate ASICs/ modem ASIC implementation in complex VLSI, experience with high speed, low power designs with proficiency in front end tools and methodologies, various CPU architectures with prior experience with CPU & IP Integration PCIe controllers, DDR memory controllers, DMAs, high speed interfaces, SoC bus protocols, emulation/Co-validation and Physical Design leading to tape-out, DFT methodologies, placement and route, clock tree synthesis, gate-level simulations, STA and timing sign-off.
- Minimum education level required: MSEE with min of ten years work experience, PhD with five years of work experience.
- Extensive knowledge of System on Chip (SOC) with multi-core processors, Verilog, SystemVerilog, and standard scripting languages utilized in ASIC design tool-chain
- C/ C++ programming is a plus
- Ability to work with a multi-site team