MIPS Architecture & Technology

Most Efficient RISC Architecture

Based on a heritage built over more than three decades of constant innovation, the MIPS architecture is the industry’s most efficient RISC architecture, delivering the best performance and lowest power consumption in a given silicon area.

MIPS32 Architecture

The MIPS32 architecture is a highly performance-efficient industry standard architecture that is at the heart of billions of electronic products, from tiny microcontrollers to high-end networking equipment. The MIPS32 architecture incorporates important functionality including SIMD (Single Instruction Multiple Data) and virtualization. These technologies, in conjunction with technologies such as multi-threading (MT), DSP extensions and EVA (Enhanced Virtual Addressing) enrich the architecture for use with modern software workloads which require larger memory sizes, increased computational horsepower and secure execution environments.

Documentation

MIPS Instruction Set Quick Reference

MIPS32 Instruction Set Quick Reference v1.01

MIPS32 Architecture for Programmers: Release 6

Introduction to the MIPS32 Architecture v6.01

The MIPS32 Instruction Set v6.06

Introduction to the microMIPS32 Architecture v6.0

The microMIPS32 Instruction Set v6.05

The MIPS32 and microMIPS32 Privileged Resource Architecture v6.02

MIPS32 Architecture for Programmers: Release 1-5

Introduction to the microMIPS32 Architecture v5.03

The MIPS32 Instruction Set v5.04

The microMIPS32 Instruction Set v5.04

The MIPS32 and microMIPS32 Privileged Resource Architecture v5.05

MIPS64 Architecture

The MIPS64 architecture has been used in a variety of applications including game consoles, office automation and set-top boxes. It continues to be popular today in networking and telecommunications infrastructure applications, and is at the heart of next-generation servers, advanced driver assistance systems (ADAS) and autonomous driving SoCs. The MIPS64® architecture provides a solid high-performance foundation for future MIPS processor-based development by incorporating powerful features, standardizing privileged mode instructions, supporting past ISAs, and providing a seamless upgrade path from the MIPS32 architecture.

Documentation

MIPS64 Architecture for Programmers: Release 6

Introduction to the MIPS64 Architecture v6.01

The MIPS64 Instruction Set v6.06

The microMIPS64 Instruction Set v6.05

The MIPS64 and microMIPS64 Privileged Resource Architecture v6.03

MIPS64 Architecture for Programmers: Releases 1-5

Introduction to the MIPS64 Architecture v5.04 (1.27 MB)

Introduction to the microMIPS64 Architecture v5.03

The MIPS64 Instruction Set v5.04

The microMIPS64 Instruction Set v5.04

The MIPS64 and microMIPS64 Privileged Resource Architecture v5.04

nanoMIPS Architecture

Designed for embedded devices, nanoMIPS is a variable length instruction set architecture (ISA) offering high performance in substantially reduced code size – it can deliver up to 40% smaller code than MIPS32.

Documentation

nanoMIPS™ Base ISA Technical Reference Manual

nanoMIPS™ Multithreading Technical Reference Manual

nanoMIPS™ DSP Technical Reference Manual

32-bit Privileged Resource Architecture Technical Reference Manual

 

MIPS Multithreading

MIPS delivers hardware multi-threading in several families of CPU IP products, providing a differentiated and highly efficient mechanism to achieve higher levels of performance and/or low latency context switching behavior.

Documentation

MIPS MT Module for the MIPS32 Architecture 01.12

MIPS MT Module for the microMIPS32 Architecture 01.12

MIPS MT Principles of Operation 01.02

An Overview of MIPS Multi-Threading

MIPS Virtualization

Hardware virtualization provides the foundation for MIPS multi-domain security technology, which ensures that applications that need to be secure are effectively and reliably isolated from each other, as well as protected from non-secure applications.

Documentation

MIPS Architecture for Programmers

Virtualization Module of the MIPS32 Architecture 01.06

Virtualization Module of the MIPS64 Architecture

Virtualization Module of the microMIPS32 Architecture 01.06

Virtualization Module of the microMIPS64 Architecture 01.06

MIPS SIMD

MIPS SIMD (Single Instruction Multiple Data) improves performance by allowing efficient parallel processing of vector operations.

Documentation

MIPS Architecture for Programmers

The MIPS32 SIMD Architecture Module

The MIPS64 SIMD Architecture Module

MIPS SIMD White Paper

MIPS SIMD Programming White Paper

MIPS DSP

Many consumer, industrial, automotive, and other products require an increasing amount of signal and media processing horsepower. DSP functionality is available as part of the standard MIPS architecture to provide a single design environment that leverages a common tool set and knowledge base.

Documentation

MIPS32 DSP ASE Instruction Set

MIPS32 DSP ASE Instruction Set Quick Reference

MIPS Architecture for Programmers

The MIPS DSP Application-Specific Extension to the MIPS32 Architecture v3.01

The MIPS DSP Application-Specific Extension to the MIPS64 Architecture v3.02

The MIPS DSP Application-Specific Extension to the microMIPS32 Architecture v3.01

The MIPS DSP Application-Specific Extension to the microMIPS64 Architecture v3.02

MIPS MCU

The MCU architecture module for MIPS has been developed to extend the interrupt controller support, reduce the interrupt latency and enhance the I/O peripheral control function typically required in microcontroller system designs. It was first implemented on the MIPS32 M14K family of processor cores, and is now a part of the microAptiv, M51xx, and M62xx core families. The MCU module supports both MIPS32 and microMIPS Instruction Set Architectures (ISAs).

Documentation

MIPS Architecture for Programmers

The MCU Application Specific Extension to the microMIPS32 Architecture

The MCU Application Specific Extension to the MIPS32 Architecture

MIPS16e

MIPS16e enables embedded system designers to reduce costs by decreasing the size of memory required to run their application by up to 40 percent compared to traditional 32-bit software implementations. In addition to providing advanced code density, MIPS16e also achieves a high level of power efficiency, and performance equivalent to that of 32-bit only implementations. MIPS16e also improves instruction cache hit rate. It is supported by hardware and software development tools from MIPS and other providers.

Documentation

MIPS32 Architecture for Programmers

MIPS16e2 Application-Specific Extension Technical Reference Manual

The MIPS16e™ Application-Specific Extension to the MIPS32®Architecture

microMIPS

Designed for microcontrollers and other small footprint embedded devices, microMIPS is a code compression instruction set architecture (ISA) that offers 32-bit performance with 16-bit code size for most instructions. It maintains 98% of MIPS32 performance while reducing code size by up to 25%, translating to significant silicon cost savings. With smaller memory accesses and efficient use of the instruction cache, microMIPS also helps to reduce system power consumption.

Proven MIPS Innovation

MIPS is an intellectual property licensing business within Wave Computing, providing processor architecture and core IP.

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AI Cores

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MIPS Architecture

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Award-winning Technology

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