Wave’s AI IP platform incorporates a comprehensive set of technology building blocks that can be scaled to specific deep learning use case requirements.
IP and Processors for Smart Edge Designs
A Unified AI Platform from the Edge to the Datacenter
Wave’s AI IP platform features a unique combination of AI engines for achieving the right balance of flexibility, performance, efficiency and cost.
AI networks requiring low latency, high throughput, concurrent and efficient execution.
Multi-threaded, Multi-core, Multi-cluster CPUs, Multi-tile dataflow cores
Complete AI Technology Building Blocks
Wave AI IP SoC Platform
Rich family of multi-core, multi-threaded, multi-cluster MIPS CPUs.
Extend the CPU families with efficient DSP, SIMD VLIW using standard instructions sets.
Wave’s patented scalable dataflow platform of processing engines.
MIPS Processor Cores
MIPS offers a comprehensive portfolio of low-power, high-performance 32- and 64-bit processor IP cores, ranging from high-end mobile applications processors to extremely small cores for deeply embedded microcontrollers.
M-Class Product Family
M-Class cores are ideal for micro-controller and embedded-type applications such as industrial controllers, Internet of Things (IoT), wearables, wireless communications, automotive and storage. M-Class line-up offers both micro-controller (MCU) and microprocessor (MPU) versions. One of the key features of the family includes hardware virtualization that provides a foundation for MIPS multi-domain security leading to the highest level of security for any embedded micro-controller architecture.
I-Class Product Family
MIPS 32-bit/64-bit I-Class cores are designed for the next generation of high-performance wireless communications, networking, automotive and AI applications. I-Class cores provide highly efficient, scalable, parallel processing performance, designed upon a foundation of hardware multi-threading and multi-core cluster CPU technologies. The latest MIPS I-class core also implements the I7200 nanoMIPS™ instruction set architecture (ISA), a new version of MIPS ISA designed to deliver best in class small code size without sacrificing performance.
P-Class Product Family
MIPS P-Class family, which ranges on the high-end of the MIPS performance spectrum, is being used for connected consumer electronics, supercomputer and HPC applications. The MIPS P-class CPU is based on a wide issue, deeply out-of-order (OoO) implementation, supporting up to six cores in a single cluster with high performance cache coherency. Complementing this raw horsepower, the P-Class family of cores includes a 128-bit integer and floating point SIMD processor, hardware virtualization, and larger physical and virtual addressing capabilities.
MIPS Aptiv Cores
MIPS microAptiv is the smallest, lowest-power CPU family available. The microAptiv cores also have higher performance than competing converged microcontroller/DSP solutions in their class.
MIPS interAptiv is a family of multi-core, multi-threaded 32-bit processors. The MIPS interAptiv CPU family of processors gives designers access to two virtual processing elements (VPEs), or hardware threads, which appear as two complete processors within a symmetric multiprocessing (SMP) operating system.
proAptiv CPUs are based on a wide issue, deeply out-of-order (OoO) implementation of the MIPS32 architecture and are available in single or multi-core product versions supporting up to six cores.
MIPS Classic Cores
MIPS Classic Cores target every level of performance needed to support any embedded use case from entry-level to high-performance — whether it be digital consumer, broadband access and networking, or state-of-the-art communications.